SimpleSolver Boolean vs. Logic Design Auto /  !  *  &  &&  +  |  ||  #  \$  ^
 Minimizer Algorithms

Boolean logic (or Boolean algebra) minimization generally follows a Karnaugh map approach, also known as a Veitch diagram, K-map, or KV-map.  The Boolean Minimizer software uses both Quine-McCluskey and Espresso(© UC Berkeley) algorithms to implement Karnaugh mapping and to optimize minimization.

In contrast, the Logic Minimizer software performs automated logic design by searching for circuits that match the transfer function specified by the input and output signal waveforms.  Because the search begins with the smallest number of gates or flip-flops, the first circuit solution found will generally be the simplest possible solution.

 Function Boolean Logic Design - Auto Input Boolean Equation yes Boolean tool "Logic Design" output Operators not and or nand nor xor xnor " Operator Formats VHDL PALASM ABEL C " Truth Table / Waveform Truth Table Waveform Variables / Input Signals 1 - 20 1 - 10 Logic States 0, 1, x 0, 1, x, r, f Minimization Combinational logic yes yes Sequential logic - yes Synchronous logic - yes Asynchronous logic - yes Minimization method Quine-McCluskeyEspresso Iterative search & compare Output Boolean Equation not and or inv and or nand nor xor xnor  dff Truth Table / Waveform Truth Table Waveform Logic Schematic Drawing - inv and or nand nor xor xnor  dff Speed Very Fast Fast to Very Slow