The Logic Designer Draw Simulation tool (LDD SIM) can be used to simulate Logic Designer Draw logic circuits. It performs the same simulation functions as the Logic Simulation (SIM) tool.
However, because LDD is a graphical WYSIWYG tool that is much easier to use than SIM, LDD/LDD SIM is generally recommended for new SimpleSolver users and large designs.
Note that LDD and SIM design files are compatible - that is an LDD design file can be opened and edited by SIM and vice-versa.
LDD SIM has two modes of operation - Hardware (HW) and Software (SW). While both modes perform functional simulations of logic circuits, the HW mode performs additional timing checks including flip-flop setup/hold times, race conditions and spike/glitch detection which are generally not applicable to software solutions.
LDD SIM uses the same simulator as the Logic Simulator tool (SIM) and will support all logic types: Combinational, Sequential, Synchronous and Asynchronous
» Flip-flop state initialization
» Optional spike/glitch filters
» 0 1 x r f logic states
1. INPUT SIGNALS & COMPARISON WORDS
A typical simulation includes a list of one or more input signals followed by one or more Comparison Words. Each input signal has a name and a waveform, a list of 1, 0, x, r, f bits.
Comparison Words are used to test the simulation result. If all bits of the signal(s) connected to the output pin match the bits of the comparison words, the simulator will report "Circuit Output meets the Input specification". If any of the bits do not match, the simulator will report "Output mismatch at tic n" where 'n' is the number of the first incorrect bit.
If you don't want to test the simulation result, set the comparison word(s) to all 'x'
Comparison Word(s) and the Output connector names can also be Name Groups of 1-4 signals. Refer to "Name Groups" in the Logic Designer Draw Help file. For a Name Group, Waveform bits must be specified in hexadecimal (characters 0-F) or the don't care character 'x'.
Combinational vs. Sequential logic
Simulation results normally include a line that says "COMBINATIONAL logic" or "SEQUENTIAL logic". If the input signals and the comparison word indicate that memory (D flip-flops or gate latches) is needed in the circuit, "SEQUENTIAL logic" is displayed. If memory is not required, "COMBINATIONAL logic" is displayed which means that D flip-flops and gate latches are not needed (even if they are included in the circuit being simulated). For example:
Input 1 0 0 0 ;
Input 2 0 1 1 ;
Comparison word 0 1 0 ;
Since the second and third input pairs are identical (0 1, 0 1) but the comparison word result is different (1, 0), a combinational solution is not possible and memory is required ("SEQUENTIAL logic").
Note that if the comparison word has no '1's or '0's, the digital logic type cannot be determined and the "COMBINATIONAL logic / SEQUENTIAL logic" display is inhibited.
Logic States - Signals
(9) logic states are supported for un-grouped signals/comparison words. The following table lists two or more characters that represent each state:
|Logic 0||0 _||logic 0|
|Logic 1||1 =||logic 1|
|Logic X||x X|| Input Signal: unknown (0 or 1)
Comparison Word: Don't care
|Rising||r R /||logic 0 to logic 1 transition|
|Falling||f F \||logic 1 to logic 0 transition|
|Spike High||h H||glitch/spike high: logic 0 to 1 to 0|
|Spike Low||l L||glitch/spike low: logic 1 to 0 to 1|
|Spike Unknown||u U||glitch/spike unknown: (high or low)|
|Oscillation||o O ~||logic 0/1 oscillation|
The following rising/falling sequences are NOT allowed: 0f, 1r, xr, xf, rx, fx, rf, fr. In addition, a signal waveform cannot begin or end with 'r' or 'f'.
Logic States - Signal Groups
For Input-signal and Comparison-word Groups, logic states are specified in Hexadecimal (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F) or an 'x'/'X" for don't care bits. R/F/H/L/U/O states are not supported.
If the Expand Hex option is checked, Input-signal, Output-signal and Comparison-word Groups are shown as Logic 0/1/x's. In the Hardware mode, Spike/Oscillation (Logic H/L/U/O) states are also shown for Output-signal Groups.
|Logic 0/1/x||0-F, X||Grouped logic 0/1/x's|
|Logic 0||0 _||Expand - logic 0|
|Logic 1||1 =||Expand - logic 1|
|Logic X||x|| Expand - Input Signal: unknown (0 or 1)
Expand - Comparison Word: Don't care
|Spike High||h||Expand - Output glitch/spike high: logic 0 to 1 to 0|
|Spike Low||l||Expand - Output glitch/spike low: logic 1 to 0 to 1|
|Spike Unknown||u||Expand - Output glitch/spike unknown: (high or low)|
|Oscillation||~||Expand - Output logic 0/1 oscillation|
When Timing waveforms are displayed in the Output Circuits/Timing window, the Signal Probe box is also displayed.
By clicking on any signal waveform in the Output section, the logic state of the signal is shown on a tic-by-tic basis. All states are supported: 0, 1, x (unkown), rising, falling, oscillation, etc.
For signal groups - such as A(0:3) - the hexadecimal value is converted to decimal. If a group has more than 4 bits - such as A(0:3) A(4:7) - the decimal value of the entire group - A(0:7) - is calculated.
If the entire group is negative (the most-significant bit - A(7) - is a '1') for a signed-number application, both the positive unsigned value and negative signed values are displayed. Refer to the following example:
| Decimal |
|1||19||37||122||140 [-116]||175 [-81]|
Options can be edited by pressing the blue 'Options' button. After exiting the Edit Options window, option changes can be un-done or re-done using the UnDo/ReDo buttons on the main LDD window.
|NO_FF_INItialize1||1-8 flip-flops - All combinations of flip-flop 0/1 starting states must meet the Compare word(s).
If any combination fails, the simulation stops at that flip-flop state combination.
Note: If all combinations work, the simulation stops at the last initialization state (all '0's).|
9+ flip-flops - All flip-flops are initialized to an 'x'.
|NO_GLITches2||HW mode - All signals in the circuit are monitored for glitches|
|SW mode - Not applicable|
|NO_OUTPUT_GLITch||HW mode - The first Output signal of the circuit is monitored for glitches|
|SW mode - Not applicable|
|WAVEFORM_0||Timing Format Off|
|WAVEFORM_1||Timing Format 01x|
|WAVEFORM_2||Timing Format _=x|
|WAVEFORM_33||Timing Format Graphic|
1. Normally (without the NO_FF_INItialize option), flip-flops are initialized using one of two methods, depending on the number of flip-flops in the design:
For 1-8 flip-flops, all combinations of flip-flop 0/1 starting states are tried, stopping at the first combination that meets the Compare word. For example if there are two flip-flops, they are started at 0 0, then 0 1, then 1 0, and then 1 1. If no combination works, the simulation displays the last initialization state tried (all '1's).
For 9+ flip-flops, all flip-flops are normally initialized to a '0'.
When NO_FF_INItialize is specified, the Comparison word typically should be an 'x' until one or more positive clock edges occur. This option only applies to D flip-flops. Gate latches are never initialized.
2. Lower-case letters are not required, NO_GLIT = NO_GLITches etc.
3. Default option
Waveforms can be edited by pressing the blue 'Waveforms' button.
Waveforms cannot be added to or deleted from the list shown and must correspond to the name in the left-hand column. (To add signal name/waveform pairs, use Edit Signals/Add in the main LDD window).
The length of the waveforms can be increased or decreased within the range of 1-1024 characters. Note: All waveforms must be of equal length. If the number of characters is different, the shorter waveforms will be filled out with "x"s.
If Name Groups are used, waveform bits must be specified in hexadecimal (characters 0-F) or the don't care character 'x'. Refer to "Name Groups" in the Logic Designer Draw Help file.
Spaces between characters may be added to improve readability.
After exiting the Edit Waveforms window, waveform changes can be un-done or re-done using the UnDo/ReDo buttons on the main LDD window.
The Search box can be used to highlight signal names, numbers or text in the Output window. To search, enter the text to be found and then depress the Enter key. This will highlight up to 100 instances of the Search text.
To clear all highlighting, delete all text in the Search box and depress Enter.
4. OUTPUT OPTIONS
Input Signals - Input signals and the Comparison word are re-drawn in the Output window without circuit simulation. This can be used to reformat IN_OUT_SIGNALS or to obtain a waveform printout. The default Timing Format for Input Signals is Graphic.
Comments - The Design Comments (if any) for the Logic Circuit are displayed.
Boolean Eqn - The Boolean equation of the circuit is displayed. This option is available only for circuits with one output and no Macro/MSI parts.
! && || - If this box is NOT checked, Boolean equation Not And Or operators are displayed as "not", "and" and "or". If this box IS checked, Boolean equation Not And Or operators are displayed as "!" "&&" and "||"
Netlist - The Parts and the Netlist of the Logic Circuit are displayed.
Logic Circuit - The Logic Circuit is graphically displayed.
Note: To save logic circuit graphics, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.
Logic Circuit Zoom: (+) (100%) (-)
Zoom In (+) Zoom 100% Zoom Out (-) - Applies only to MSI/Macro Circuits
Timing Format - Timing waveform outputs can be turned Off or formatted in one of three formats:
Off - No waveforms displayed (except for the Input Signals option)
01x - Logic 0, 1, x format
_=x - Logic 0 (underscore), Logic 1 (equal), x format
Graphic - Graphical format of 0, 1, x, rising and falling states including glitches/spikes.
Note: To save graphic waveforms, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.
Input Spec - The timing format is controlled by WAVEFORM_0|1|2|3 Options in the Input Specification. If there is no WAVEFORM_n Option in the Input Spec, the default Timing Format is Graphic.
Expand Hex - Name groups with hexadecimal bit-patterns are expanded to seperate name/bit-pattern lines.