If a synchronous circuit has one or more asynchronous input signals, each input should be synchronized. Otherwise, the circuit will be subject to flip-flop spikes and/or oscillations.
Whenever there are setup and hold time violations in a flip-flop, it enters a state where its output is unpredictable. The flip-flop may set, reset, spike high, spike low, or oscillate.
This oscillation is called "Metastability" and will be a likely cause of intermittent system failures.
Note that Metastability is an instance of the "Buridan's ass" paradox.
Refer to the following articles:
1. Synchronizing Filter
Each asynchronous input signal should be synchronized and filtered for spikes and oscillations.
A circuit with two or more flip-flops in series, as shown below, is recommended. Note that the period of the "clock" signal must be greater than the duration of the metastable oscillation.
This circuit, Metastable-Sync filter.txt, is available in the LDD, Sim and SYN Examples folders.
2. Single-Point Filter
Each asynchronous input signal should be synchronized and filtered one-time only. Multiple filters of the same signal can generate out-of-phase signals which could cause system failures.
3. Latency Estimates
Note that the synchronizing filters will cause a delay(latency) of the input signals. A rule of thumb is that a 2-flip-flop synchronizer will cause up to two clock cycles of delay to the synchronized signal.