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Logic Simulation Help

Logic Simulator

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The Logic Simulation tool (SIM) can be used to design and simulate digital logic circuits.  It performs many of the same functions as the Logic Design Draw (LDD) tool.

However, because LDD is a graphical WYSIWYG tool that is much easier to use, LDD is generally recommended for new SimpleSolver users and for large designs.

Note that LDD and SIM design files are compatible - that is an LDD design file can be opened and edited by SIM and vice-versa.

The SIM Input Specification window contains the description of the logic circuit to be simulated.  Data can be typed in, pasted, loaded from a file (File/Open or Examples menus), or a file can be dragged-and-dropped onto the Input window.  File data must be in standard ASCII text format.

SIM has two modes of operation - Hardware (HW) and Software (SW).  While both modes perform functional simulations of logic circuits, the HW mode performs additional timing checks including flip-flop setup/hold times, race conditions and spike/glitch detection which are generally not applicable to software solutions.

SIM uses the same simulator as Logic Design Draw (LDD) and Logic Design Auto (SYN) and will support all logic types:

Combinational
Sequential
Synchronous
Asynchronous

Simulation features
- basic part types: buf, and, or, nand, nor, xor, xnor logic gates and D flip-flops
- RAM read-write memory
- 54/74LS series MSI functions such as: LS138, LS148, LS151, LS153, LS157, LS163, LS164, LS181, LS193, LS194
- Flip-flop state initialization
- Optional spike/glitch filters
- 0 1 x r f logic states

Most simulation features of SIM are identical to the Logic Design Auto tool.  However SIM requires the circuit to be pre-defined using a PARTS and a NETLIST section.

GETTING STARTED

Example
The following example is from file "2-input AND NL.txt" which can be loaded from the Primitive Examples menu:

PARTS    and   output
NETLIST  1,2      3

IN_OUT_SIGNALS
  A  0101;   ' input #1
  B  0011;   ' input #2
  C  0001;   ' comparison word

The PARTS section specifies one and gate.  The output pin of the circuit is specified by the word "output".  This word is optional but the corresponding Netlist number for the output (3) is required.

The NETLIST section connects inputs 1 and 2 to the and gate (1,2), and connects the and gate output (3) to the output pin.

Note that 1-50 signals can be connected to the output pin/connector.  For example, if the number 1 is added to the Netlist (NETLIST 1,2   3,1)  the output connector will have two inputs: the output of the AND gate and Input signal A.

Note also that input signals are numbered from 1..n and that part numbering starts at n+1.

The IN_OUT_SIGNALS section  can list up to 50 input signals and their bit patterns plus one or more comparison words.

For this example A and B are inputs, C  is the comparison word. The bit pattern of C is specified as  the logical 'AND' of A and B.

The comparison word is used to  test the simulation result.  If all bits of the signal connected  to the output (in this case the 'and' gate) match the bits  of the comparison word, the simulator will report "Circuit  Output meets the Input specification".   If any of the bits do  not match, the simulator will report "Output mismatch at tic  n" where 'n' is the number of the first incorrect bit.

If you  don't want to test the result, set the comparison word to all  'x' (in this case "C xxxx;").

Circuit simulation is started by clicking the "Go" button.

The circuit is shown in the Output Circuits / Timing window if Logic Circuit is checked.

Similarly, the Boolean equation is displayed in the Output Circuits / Timing window if Boolean Eqn is checked.

The truth table or waveform of the circuit is also shown unless the Timing Format is "Off".


Other Examples
Other files in the Examples: directories demonstrate the flexibility of SIM as well as usage of its Advanced Options.  For example:

    "Adder with OR2 NL.txt" is a 14-part combinational circuit.

    "DFF Edge-Triggered NL.txt" is an asynchronous edge-triggered D-flip-flop using Nand gates.

    "Serial Input 32-bit NL.txt" illustrates a relatively complex sequential circuit specification.

   "54LS163 4-bit counter.txt" is an MSI part sequential circuit with (38) parts.


ADVANCED FEATURES and OPTIONS


1.    INPUT SPECIFICATION SECTIONS

There are five sections of a Design Specification, two of which are optional.

IN_OUT_SIGNALS   Required - A list of the Input signals & the Comparison word(s).  The comparison word(s) must be last in the list.  At least one item, a comparison word, must  be specified.
PARTS Required (unless there are no parts) - A complete list of parts for the circuit to be simulated.  Following the list of parts is an optional Output signal name.  If the Output signal is omitted, the default name for the output is "output".
NETLIST Required - Numbers corresponding to inputs to the circuit parts and inputs to the output pin.  At least one Netlist number or state (H, L, X) must be specified.
OPTIONS Optional - Used to control or check circuit simulation output
END_OF_SPEC Optional - Indicates the end of the design specification


The Input Specification can also contain comments.  Refer to the COMMENTS section below for comment syntax.


2.    INPUT SPECIFICATION - IN_OUT_SIGNALS
This section specifies the truth table or waveforms for the circuit to be simulated.  Typically one or more input signals (signal name and truth table/waveform) are followed by one or more comparison words.    Each input signal has a name followed by a waveform, a list of 1,0,x bits.  The last name(s) in the list is the comparison word(s).  Each name-truth table/waveform pair must be terminated with a semi-colon ";"

Names

Names can be any word from 1-32 characters long with the following exceptions:

a. SIM/SYN Section names (IN_OUT_SIGNALS, PARTS, NETLIST, OPTIONS, END_OF_SPEC) are not allowed as signal names

b. Names consisting only of numbers, such as "123", are not allowed; this avoids Signal Name and Netlist number confusion

c. The following characters not allowed in a name: space tab ; : " or character(s) beginning a comment: // -- ' # .   In addition "=" is not allowed for the Output signal.

Name Groups

A Name group can be used to generate from 1 to 4 numbered names and bit-patterns.  The logic states of the bit-patterns must be specified in hexadecimal format, that is characters 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F (decimal values of 0-15).

Name groups are defined for Input signals and the Compare Words by adding "(n:m)" to the end of the name, where 'n' is the starting bit and 'm' is the last bit of the group.
Note: If the Output connector has more than (1) input, a name group is automatically generated for the Output signals during simulation.

Example:

IN_OUT_SIGNALS

   A(0:3)  4 D A 3 1 0;

This will generate signals A(0), A(1), A(2), A(3), each of which can have unique logic 0/1 bit patterns.

Note that the smallest group number, A(0), is the least-significant hexadecimal bit; and that only Logic 0, Logic 1 and Logic x states are supported.  If an 'x' is specified, the hexadecimal (unexpanded) value of the four signals will be an 'x' for that bit/tic time.

If the Timing Format "Expand Hex" box is checked, the Output display will show the four signals separately:

IN_OUT_SIGNALS

   A(0)   0 1 0 1 1 0;

   A(1)   0 0 1 1 0 0;

   A(2)   1 1 0 0 0 0;

   A(3)   0 1 1 0 0 0;

Primitive Example "Decode IR.txt" can be run as an example of a Name Group and Hexadecimal bit patterns.

Combinational  vs. Sequential logic

Simulation results normally include a line that says "COMBINATIONAL logic" or "SEQUENTIAL logic".  If the input signals and the comparison words indicate that memory (D flip-flops or gate latches) is needed in the circuit, "SEQUENTIAL logic" is displayed.  If memory is not required, "COMBINATIONAL logic" is displayed which means that D flip-flops and gate latches are not needed (even if they are included in the circuit being simulated).   For example:

   Input 1                  0  0  0 ;

   Input 2                  0  1  1 ;

   Comparison word  0  1  0 ;

Since the second and third input pairs are identical (0 1, 0 1) but the comparison word result is different (1, 0), a combinational solution is not possible and memory is required ("SEQUENTIAL logic").

Note that if the comparison word has no '1's or '0's, the digital logic type cannot be determined and the "COMBINATIONAL logic / SEQUENTIAL logic" display is inhibited.

Logic States - Signals

(9) logic states are supported for un-grouped signals/comparison words.  The following table lists two or more characters that represent each state:

Logic State Character Description
Logic 0 0 _     logic 0
Logic 1 1 =     logic 1
Logic X x X     Input Signal: unknown (0 or 1)
    Comparison Word: Don't care
Rising r R /     logic 0 to logic 1 transition
Falling f F \     logic 1 to logic 0 transition
Spike High h H     glitch/spike high:  logic 0 to 1 to 0
Spike Low l L     glitch/spike low:  logic 1 to 0 to 1
Spike Unknown  u U     glitch/spike unknown: (high or low)
Oscillation o O ~     logic 0/1 oscillation

The following rising/falling sequences are NOT allowed: 0f, 1r, xr, xf, rx, fx, rf, fr.  In addition, a signal waveform cannot begin or end with 'r' or 'f'.

Logic States - Signal Groups

For Input-signal and Comparison-word Groups, logic states are specified in Hexadecimal   (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F) or an 'x'/'X" for don't care bits.  R/F/H/L/U/O states are not supported.

If the Expand Hex option is checked, Input-signal, Output-signal and Comparison-word Groups are shown as Logic 0/1/x's.   In the Hardware mode, Spike/Oscillation (Logic H/L/U/O) states are also shown for Output-signal Groups.

Logic State   Character  Description
Logic 0/1/x 0-F, X     Grouped logic 0/1/x's
Logic 0 0 _     Expand - logic 0
Logic 1 1 =     Expand - logic 1
Logic X x     Expand - Input Signal: unknown (0 or 1)
    Expand - Comparison Word: Don't care
Spike High h     Expand - Output glitch/spike high:  logic 0 to 1 to 0
Spike Low l     Expand - Output glitch/spike low:  logic 1 to 0 to 1
Spike Unknown  u     Expand - Output glitch/spike unknown: (high or low)
Oscillation ~     Expand - Output logic 0/1 oscillation
Signal Probe

When Timing waveforms are displayed in the Output Circuits/Timing window, the Signal Probe box is also displayed.

By clicking on any signal waveform in the Output section, the logic state of the signal is shown on a tic-by-tic basis.  All states are supported: 0, 1, x (unkown), rising, falling, oscillation, etc.

For signal groups - such as A(0:3) - the hexadecimal value is converted to decimal.  If a group has more than 4 bits - such as A(0:3) A(4:7) - the decimal value of the entire group - A(0:7) - is calculated.

If the entire group is negative (the most-significant bit - A(7) - is a '1') for a signed-number application, both the positive unsigned value and negative signed values are displayed.  Refer to the following example:

tic   1    2     3   4   5   6 
A(0:3)   1   3   5 A C F
A(4:7)   0   1   2 7 8 A
Decimal
Value
  1 19 37 122 140 [-116] 175 [-81]

3.    INPUT SPECIFICATION - PARTS
This section is required unless the circuit has no parts.  The circuit output can be connected directly to an input signal or to a logic high (H), low (L) or don't care (X).  However simulation of a circuit without parts is not particularly useful.

Part Types
There are 15 primitive types supported

   Logic gates: buf inv  and or xor nand nor xnor
   D flip-flops: dff   dff_c   dff_cp
   Oscillators: osc2, osc4, osc6, osc8

The output pin of the circuit can be specified by adding the word "output" to the end of the Parts list.  This word is optional but the corresponding Netlist number for the output pin is required.  To specify an Output signal name other than "output", the format is "conn_x...x" where "x...x" is the Output signal name.

The buf (buffer) and inv (inverter) parts have (1) input while and, or, xor, nand, nor, xnor gates have (2) inputs.

The buffer part is non-inverting and can be used to cause skew (delay) on one or more signals.  Primitive example " 2-input AND with input B delayed NL.txt" illustrates the effect of delaying one circuit input; the skew between signals A and B results in output glitches.

The and, or, xor, nand, nor, xnor gates can also have from 3 to 10 inputs by appending the number of inputs to the part name - for example, and3, or4, nand5, nor10.

The dff is a D flip-flop with only a D and Clock input.   The dff_c is a dff plus a /Clear input.   The dff_cp is a dff plus /Clear and /Preset inputs.

Oscillators: osc2, osc4, osc6, osc8.  These parts are free-running square-wave generators, with a period of 2, 4, 6 or 8 simulation 'tic' times.

Macro and MSI (Medium Scale Integration) parts include rom and ROM4 (read-only memory), ram and RAM4 (read-write memory), jkff (JK flip-flop), LS74 D flip-flop, LS138 3:8 decoder, LS148 encoder, LS151/3/7 multiplexers, LS163 4-bit counter, LS164 8-bit shift register, LS181 4-bit ALU, LS193 4-bit up-down counter, LS194 register.

Read-Only-Memory (ROM) data:
To specify data for a rom part (256x1), add "_data" to the part name, where "data" is binary (0/1/x).  For example, rom_0100 specifies rom addresses 0,1,2,3 to have a logic 0,1,0,0.
To specify data for a ROM4 part (256x4), add "_data" to the part name, where "data" is hexadecimal (0-F).  For example, ROM4_0FA5 specifies rom addresses 0,1,2,3 to have 4-bit data of 0,F,A,5.

Refer to Logic Parts Data for part descriptions and function tables.

Part Quantities
Part quantities can be specified separately or as a group.  For example,

   "and and and xor"
        or
   "and=3 xor"
        or
   "and xor and=2"

specify three "and" gates & one "xor" gate.


4.    INPUT SPECIFICATION - NETLIST
This section is required.  The Netlist is a list of numbers that specify the circuit wiring, that is the connections between the input signals, parts and output pin.

Netlist numbers 1..n represent input signals 1..n.  Netlist numbers n+1..m represent parts 1..m. 

For example if there are 3 input signals and four and gates (and=4), Netlist numbers are assigned as follows:

Input/Part   Netlist #
  input1          1
  input2          2
  input3          3
  and1            4
  and2            5
  and3            6
  and4            7

The letters h/H, l/L, x/X can be used as Netlist "numbers" to specify a logic 1, 0 or x.

When specifying a Netlist for D flip-flops, the order is d, >(clock), [clr(clear)], [pre(preset)].  For example, a Netlist of 3 4 6 7 connects d=3 clock=4 clr=6 pre=7 for a dff_cp part.


5.    INPUT SPECIFICATION - OPTIONS
This section is optional. If this section is excluded or has no options, the default options (Note 3) are used.  OPTIONS can be used to control or monitor simulation results.

OPTION Description
NO_FF_INItialize1 1-8 flip-flops - All combinations of flip-flop 0/1 starting states must meet the Compare word(s).  If any combination fails, the simulation stops at that flip-flop state combination.  Note: If all combinations work, the simulation stops at the last initialization state (all '0's).

9+ flip-flops - All flip-flops are initialized to an 'x'.
NO_GLITches2 HW mode - All signals in the circuit are monitored for glitches
SW mode - Not applicable
NO_OUTPUT_GLITch  HW mode - The first Output signal of the circuit is monitored for glitches
SW mode - Not applicable
WAVEFORM_0 Timing Format Off
WAVEFORM_1 Timing Format 01x
WAVEFORM_2 Timing Format _=x
WAVEFORM_33 Timing Format Graphic

Notes:

1. Normally (without the NO_FF_INItialize option), flip-flops are initialized using one of two methods, depending on the number of flip-flops in the design:

For 1-8 flip-flops, all combinations of flip-flop 0/1 starting states are tried, stopping at the first combination that meets the Compare word(s).  For example if there are two flip-flops, they are started at 0 0, then 0 1, then 1 0, and then 1 1.  If no combination works, the simulation displays the last initialization state tried (all '1's).

For 9+ flip-flops, all flip-flops are normally initialized to a '0'.

When NO_FF_INItialize is specified, the Comparison word(s) typically should be an 'x' until one or more positive clock edges occur.  This option only applies to D flip-flops.  Gate latches are never initialized.

2. Lower-case letters are not required, NO_GLIT = NO_GLITches etc.

3. Default option

4. If SYN-only Options, such as SOLUTION_First, are included in the SIM Input Specification, they will have no effect.


6.    INPUT SPECIFICATION - END_OF_SPEC
This section is optional. If this section is excluded SIM will consider all text in the Input Specification window to be part of the specification.  If END_OF_SPEC is included, any text after it will be ignored.

7.    COMMENTS
Comments begin with "//" or "--" or " ' " or "#" and extend to the end of the line.

CAUTION: The Logic Design Draw (LDD) tool only supports comments at the beginning of the design file (before any Section names). If a SIM design file is edited by the LDD tool, any comments following the first section name will be lost.

8.    LIMITS

in signals 0-50 input signals to logic circuit or MSI part
out signals 1-50 inputs to Output connector
comparison words 1-50 data - checks the simulation result
primitive parts 0-1000 total parts per circuit
Macro parts 0-50 User-defined Macro/MSI parts
signal name 1-32 characters
signal waveform 1-1024 characters
  Search

The Search box can be used to highlight signal names, numbers or text in the Output window.  To search, enter the text to be found and then depress the Enter key.  This will highlight up to 100 instances of the Search text.

To clear all highlighting, delete all text in the Search box and depress Enter.

9.    OUTPUT OPTIONS

Input Signals - IN_OUT_SIGNALS are re-drawn in the Output window without circuit simulation.  This can be used to reformat IN_OUT_SIGNALS or to obtain a waveform printout.  The default Timing Format for Input Signals is Graphic.

Boolean Eqn - The Boolean equation of the circuit is displayed. This option is available only for circuits with one output and no Macro/MSI parts.

! && || - If this box is NOT checked, Boolean equation Not And Or operators are displayed as "not", "and" and "or".  If this box IS checked, Boolean equation Not And Or operators are displayed as "!" "&&" and "||"

Netlist - The Parts and the Netlist of the Logic Circuit are displayed.

Logic Circuit - The Logic Circuit is graphically displayed.

Note: To save logic circuit graphics, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.

Logic Circuit Zoom:    (+)  (100%)  (-)

Zoom In (+)   Zoom 100%   Zoom Out (-)     -  Applies only to MSI/Macro Circuits

Timing Format - Timing waveform outputs can be turned Off or formatted in one of three formats:

Off - No waveforms displayed (except for the Input Signals option)

01x - Logic 0, 1, x format

_=x - Logic 0 (underscore), Logic 1 (equal), x format

Graphic - Graphical format of 0, 1, x, rising and falling states including glitches/spikes.
Note: To save graphic waveforms, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.

Input Spec - The timing format is controlled by WAVEFORM_0|1|2|3 Options in the Input Specification.  If there is no WAVEFORM_n Option in the Input Spec, the default Timing Format is Graphic.

Expand Hex - Name groups with hexadecimal bit-patterns are expanded to seperate name/bit-pattern lines.