SimpleSolver

Logic Parts Help

Logic Parts Data

SimpleSolver home

1.  Primitive Parts

The first (11) Primitive parts listed below (buffer through the D flip-flops) can be used with all logic design-simulation tools:  Logic Design Draw, Logic Simulator and Logic Design Auto.  However oscillator, rom and ram parts cannot be used with Logic Design Auto.

Primitive   Output = Logic '0' Output = Logic '1'
bufferinput = '0'input = '1'
inverterinput = '1'input = '0'
and gateany input = '0' all inputs = '1'
nand gateall inputs = '1'any input = '0'
or gateall inputs = '0'any input = '1'
nor gateany input = '1'all inputs = '0'
exclusive or
gate
even number (0,2,4, ..)
of '1' inputs
odd number (1,3,5, ..)
of '1' inputs
exclusive nor
gate
odd number (1,3,5, ..)
of '1' inputs
even number (0,2,4, ..)
of '1' inputs
D flip-flopClock '0'->'1' and D='0'Clock '0'->'1' and D='1'
D flip-flop
with clear
/Clr='0'    or
Clock '0'->'1' and D='0'
/Clr='1'    and
Clock '0'->'1' and D='1'
D flip-flop
clear & preset
/Clr='0' and /Pre='1'   or
Clock '0'->'1' and D='0'
/Pre='0'    or /Clr='1' and
Clock '0'-> '1' and D='1'
oscillatorStarts at Logic '0' Free-running square wave
Period = 2/4/6/8 clock tics
rom256x1 bit
read-only memory
Refer to ROM4 (below)
for operation
ram256x1 bit
read-write memory
Refer to RAM4 (below)
for operation


D flip-flop
Operation

There are three D flip-flop primitives: dff, dff_c, dff_cp. The dff is a D flip-flop with only a D and Clock input.   The dff_c is a dff plus a /Clear input.   The dff_cp is a dff plus /Clear and /Preset inputs.

These flip-flop primitives operate like the classic TTL 5474/7474 D-type flip-flop.  The flip-flops are positive edge-triggered, that is they change state when the clock input rises from a logic 0 to a logic 1.  The /Clear and /Preset inputs are active at a logic 0 level.

The flip-flops require a positive amount of Setup Time, that is the D input must be stable at least one time tic before the clock rises.  Similarly the /Clear and /Preset inputs must be inactive (Release Time) for at least one time tic before the clock rises ( ^ ).  One time tic is defined as the time from one waveform 0/1/x/r/f character to the next.

Flip-flop parts also require at least "0" Hold Time, that is the D input must not change until the clock rises.  To meet this Hold Time requirement, the D input may change simultaneously with the clock but it may not change even one gate-delay before the clock rises.

Any Setup, Release, or Hold Time violation results in a flip-flop going to the 'x' state.

Oscillator
Operation

There are four oscillator primitives: osc2, osc4, osc6, osc8.  These parts are free-running square-wave generators, with a period of 2, 4, 6 or 8 simulation 'tic' times.

Each 'osc' part has no inputs and one output.

For most designs, only one 'osc' part should be needed.

2.  MSI Parts

The following MSI parts, which contain multiple primitive parts, can be used only with Logic Design Draw and Logic Simulator.  Many of the MSI functions are from the 54/74LS circuit series.

Symbols used in the MSI tables are described below:

Table Symbols

Symbol Description
L Logic 0
H Logic 1
X Logic x
/name 0-active signal
^ Rising edge of [clock] signal
toggle Change state: L -> H  or  H -> L
no change Remain at previous logic level

ROM4

256x4 bit
Read
Only
Memory

Both the rom and ROM4 parts require their data to be defined before simulation:  When editing a rom/ROM4 part in Logic Design Draw, a "Select Data.." option is provided to define read-only data.  When using the Logic Simulator, data can be added to the rom/ROM4 part name as described in Section 3: "INPUT SPECIFICATION - PARTS" of the Logic Simulator Help file.

The rom is a 256x1 bit memory while the ROM4 is a 256x4 bit memory;  the parts are identical except for the number of internal/output bits (D/Q).

The -G input enables reading internal data to the Q output(s) from the memory location selected by the 8-bit address (A0-A7).

The rom and ROM4 input-to-output state changes are shown below:

  /G  Data
defined
 Q 
H X X
L No X
L Yes D

RAM4

256x4 bit
Random
Access
Memory

The ram is a 256x1 bit memory while the RAM4 is a 256x4 bit memory;  the parts are identical except for the number of input/output bits (D/Q).

The -G input enables writing and reading data into and out of the memory location selected by an 8-bit address (A0-A7).   If the -write (-wr) signal is low, data (D) is written into the memory and the Q output(s) is/are 'x'.   When -write goes high, the Q output(s) goes/go to the logic state(s) of the location selected by A0-A7.

The ram and RAM4 input-to-output state changes are shown below:

  /G  /write  Q 
H X X
L L X
L ^ D
L H no change

JK Flip-flop

The JK flip-flop is very similar to the 54/74LS109 part.  The only difference is that the JK flip-flop has a 1-active K input while the LS109 part has a 0-active K input (/K).
The input-to-output state changes are shown below:

/pre /clr Clock    J      K   Q /Q Notes
L H X X X H L Preset (async)
H L X X X L H Clear (async)
L L X X X H H Preset &
Clear (async)
H H ^ H L H L Set
H H ^ L H L H Reset
H H ^ H H /Q Q toggle
H H ^ L L no change no change Hold
H H L X X no change no change Hold

54LS74
D Flip-flop

The 54LS74 is very similar to the dff_cp part.  The only difference is that the 54LS74 has both Q and -Q outputs.  The input-to-output state changes are shown below:

/pre /clr Clock    D    Q  /Q  Notes
L H X X H L Preset (async)
H L X X L H Clear (async)
L L X X H H Preset &
Clear (async)
H H ^ H H L Set
H H ^ L L H Reset
H H L X no change no change Hold

54LS138
3:8 Decoder

The 54LS138 decodes one-of-eight lines dependent on the states of enables G1, /G2A, /G2B and the address lines C, B, A.   The input-to-output state table is shown below:

G1 /G2*  C  B   A  /Y0 /Y1 /Y2 /Y3 /Y4 /Y5 /Y6 /Y7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L

/G2* = /G2A + /G2B (Logical 'Or')

54LS148
8:3 Encoder

The 54LS148 features priority gating of the inputs to ensure that only the highest-order data line is encoded. The (8) inputs, /I0 to /I7, generate a 3-bit address and a strobe (/GS) to indicate which input, if any, is active. /I7 has highest priority and /I0 is lowest.  /EI (Enable Input) and /E0 (Enable Output) are provided to allow octal expansion without the need for external circuitry.   The input-to-output state table is shown below:

/EI /I0 /I1 /I2 /I3 /I4 /I5 /I6 /I7 /A2 /A1 /A0 /GS /EO
H X X X X X X X X H H H H H
L H H H H H H H H H H H H L
L X X X X X X X L L L L L H
L X X X X X X L H L L H L H
L X X X X X L H H L H L L H
L X X X X L H H H L H H L H
L X X X L H H H H H L L L H
L X X L H H H H H H L H L H
L X L H H H H H H H H L L H
L L H H H H H H H H H H L H

54LS151
8:1 Multiplexer

The 54LS151 is a multiplexer that selects one-of-eight inputs dependent on the states of the strobe/enable /G and the address lines C, B, A.   The input-to-output state table is shown below:

/G  C  B   A   Y  /Y
H X X X L H
L L L L D0 /D0
L L L H D1 /D1
L L H L D2 /D2
L L H H D3 /D3
L H L L D4 /D4
L H L H D5 /D5
L H H L D6 /D6
L H H H D7 /D7

54LS153
4:1 Multiplexer

The 54LS153 is a dual (circuits 1,2) multiplexer that selects one of four 2-bit input sources dependent on the states of the strobe/enable /G and the address lines B, A.   The input-to-output state table is shown below.  Signals /1G, 1D0-1D3, 1Y are for circuit 1 and signals /2G, 2D0-2D3, 2Y are for circuit 2.   Address lines A and B are shared between the two circuits.

/G  B   A   Y 
H X X L
L L L D0
L L H D1
L H L D2
L H H D3

54LS157
2:1 Multiplexer

The 54LS157 is a quad (circuits 1,2,3,4) multiplexer that selects one-of-two inputs dependent on the states of the strobe/enable /G and the address line A.   The input-to-output state table is shown below.   Signals 1D0, 1D1, 1Y are for circuit 1, etc.  Signals /G, and A are shared between all four circuits.

/G  A   Y 
H X L
L L D0
L H D1

54LS163A
Binary Counter

The 54LS163A is a 4-bit synchronous binary counter that can be cleared (count=0) or preset to a starting count of 0-15.   All control inputs (ENT, ENP, Load, Clear) are synchronous, that is their state changes are effective on the rising edge of the clock.   The below table illustrates the operation of the 54LS163A.  Each Q3-Q0, RC state change follows a L-to-H Clock transition.

/clr /load ENT ENP Q3 Q2 Q1 Q0 RC Notes
H H X X X X X X X startup
H L X X D3 D2 D1 D0 X Load
L X X X 0 0 0 0 0 Clear
H H H H 0 0 0 1 0 count=1
H H H H 0 0 1 0 0 count=2
H H H H 0 0 1 1 0 count=3
H H H H .. .. .. .. 0 count=n
H H H H 1 1 1 1 1 count=15

54LS164
Serial
Shift Register

The 54LS164 is an 8-bit serial-shift register.   It can be used to convert 8-bits segments of serial data to 8-bit parallel words.

The clear input (/clr) is 0-active and asynchronous, and sets the Q0-Q7 states to all logic 0's.

When /clr is inactive, each rising-edge of the clock shifts flip-flop states one position to the right: SI to Q0, Q0 to Q1, Q1 to Q2 etc.   The Q7 signal may be used to drive a second 8-bit LS164; thus LS164 counters can be cascaded to build 16-bit, 24-bit, etc. shift registers.

The below table illustrates the operation of the 54LS164.  Each Q0-Q7 state change follows a L-to-H clk transition.

/clr SIa SIb Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes
H X X X X X X X X X X startup
L X X 0 0 0 0 0 0 0 0 Clear (async)
H L X 0 0 0 0 0 0 0 0 SI=0, shift
H X L 0 0 0 0 0 0 0 0 SI=0, shift
H H H 1 0 0 0 0 0 0 0 SI=1, shift
H L X 0 1 0 0 0 0 0 0 SI=0, shift
H L X 0 0 1 0 0 0 0 0 SI=0, shift
H L X 0 0 0 1 0 0 0 0 SI=0, shift
H L X 0 0 0 0 1 0 0 0 SI=0, shift
H L X 0 0 0 0 0 1 0 0 SI=0, shift
H L X 0 0 0 0 0 0 1 0 SI=0, shift
H L X 0 0 0 0 0 0 0 1 SI=0, shift

LS181
Arithmetic
Logic Unit

The 54LS181 is a 4-bit arithmetic-logic unit (ALU) that can perform both arithmetic [clear, add, subtract, increment, decrement] and logic [not(/), and(*), or(+), xor($)] operations.

The ALU function table is shown below.  Select signals S0-S3 select 1 of 16 LOGIC functions if the Mode (M) bit is H; 1 of 16 ARITHMETIC functions if Mode (M) is L and Carry In (/Ci) is H; and second group of 1 of 16 ARITHMETIC functions if Mode (M) is L and Carry In (/Ci) is L.

The carry out (/Co) signal can be used to drive a second 4-bit LS181; thus LS181 ALUs can be cascaded to build 8-bit, 12-bit, etc. ALUs.

S3-S0
(hex)
S0 S1 S2 S3 Logic
M=H
Arithmetic
M=L  /Ci=H
Arithmetic
M=L  /Ci=L
0 L L L L F=/A F=A F=A plus 1
1 H L L L F=/(A+B) F=A+B F=(A+B) plus 1
2 L H L L F=/A*B F=A+/B F=(A+/B) plus 1
3 H H L L F=0000 F= -1 (2's compl) F=0
4 L L H L F=/(A*B) F=A plus A*/B F=A plus A*/B plus 1
5 H L H L F=/B F=(A+B) plus A*/B F=(A+B) plus A*/B plus 1
6 L H H L F=A$B F=A minus B minus 1 F=A minus B
7 H H H L F=A*/B F=A*/B minus 1 F=A*/B
8 L L L H F=/A+B F=A plus A*B F=A plus A*B plus 1
9 H L L H F=/(A$B) F=A plus B F=A plus B plus 1
A L H L H F=B F=(A+/B) plus A*B F=(A+/B) plus A*B plus 1
B H H L H F=A*B F=A*B minus 1 F=A*B
C L L H H F=1111 F=A plus A F=A plus A plus 1
D H L H H F=A+/B F=(A+B) plus A F=(A+B) plus A plus 1
E L H H H F=A+B F=(A+/B) plus A F=(A+/B) plus A plus 1
F H H H L F=A F=A minus 1 F=A

54LS193
Up-Down
Counter

The 54LS193 is a 4-bit binary up-down counter that can be cleared (count = 0) or preset to a starting count of 0-15, and then alternately count up or count down.

The clear (clr) input is 1-active, asynchronous, and sets the Q3-Q0 state to a count of 0.

The 0-active asynchronous load signal sets the state of Q3-Q0 to the bit pattern of D3-D0.

There is no clock signal, per se: the up/down signals 'clock' the Q3-Q0 flip-flops to increase/decrease the count by one.   These signals are 0-active, 'clocking' the flop-flops on their rising edge; the signal must be a H-L-H pulse, shown in the table below as '^'.   Only one up/down signal can be active at a time; when one is active, the other must be at a logic 1.

The carry out (/Co) signal and borrow out (/Bo) signals can be used to drive a second 4-bit LS193; thus LS193 counters can be cascaded to build 8-bit, 12-bit, etc. counters.

The below table illustrates the operation of the 54LS193.  Each Q3-Q0 'clocked' state change follows a L-to-H up/down transition.

 clr  /load   up    dn  Q3 Q2 Q1 Q0 /Co /Bo Notes
L H H H X X X X H H startup
L L H H D3 D2 D1 D0 H H Load (async)
H H H H 0 0 0 0 H H Clear (async)
L H ^ H 0 0 0 1 H H count=1
L H ^ H 0 0 1 0 H H count=2
L H ^ H .. .. .. .. H H count=n
L H ^ H 1 1 1 1 H H count=15
L H ^ H 0 0 0 0 ^ H count=0
L H H ^ 1 1 1 1 H ^ count=15
L H H ^ 1 1 1 0 H H count=14
L H H H no
change
no
change
no
change
no
change
H H Hold

54LS194A
Universal
Shift Register

The 54LS194A is a 4-bit bi-directional shift register that can be cleared (Q0-Q3 = 0) or preset to a Q0-Q3 state of 0-15.   The clear (/clr) input is asynchronous, while the mode control inputs  (S0, S1) are synchronous, that is their states are effective on the rising edge of the clock.   The S0 and S1 inputs provide four states of operation: load, shift right, shift left and hold (do nothing).  The below table illustrates the operation of the 54LS194A.  Each synchronous Q0-Q3 state change follows a L-to-H Clock transition.

 /clr    S0    S1  Q0 Q1 Q2 Q3 Notes
H L L X X X X startup
L X X 0 0 0 0 Clear (async)
H H H D0 D1 D2 D3 Load
H H L SRsi Q0 Q1 Q2 Shift right
H L H Q1 Q2 Q3 SLsi Shift left
H L L no
change
no
change
no
change
no
change
Hold

54LS273
8-bit
Data Register

The 54LS273 is a 8-bit data register. It has (8) D flip-flops, each with its own D input and Q output, and a common clock (clk) and clear (-clr).  The flip-flops are dff_c primitive parts, which operate as explained above in the D flip-flop Operation section.  The LS273 input-to-output state changes are shown below:

/clr Clock    D    Q  Notes
L X X L Clear (async)
H ^ H H Set
H ^ L L Reset
H L X no change Hold

ALU8
8-Bit
Arithmetic
Logic Unit

The ALU8 supports signed-integer arithmetic and bitwise logical operations.  It is similar to the 4-bit LS181 ALU, but the ALU8 is an 8-bit part and additionally has multiply, divide and mod/remainder operators.  These features make ALU8 is a key part of the LDD/SIM 8-Bit_Programmable Computer example.

ALU8 has two 8-bit inputs, A and B, and a 4-bit function select (S) input. The below table shows the 16 arithmetic/logic funtions available:

S3-S0
(hex)
S0 S1 S2 S3 Function
0 L L L L F = 0
1 H L L L F = -1
2 L H L L F = A
3 H H L L F = B
4 L L H L F = A + 1
5 H L H L F = A - 1
6 L H H L F = A + B
7 H H H L F = A - B
8 L L L H F = A * B
9 H L L H F = A / B
A L H L H F = A Mod B
B H H L H F = Not A
C L L H H F = Not B
D H L H H F = A And B
E L H H H F = A Or B
F H H H L F = A Xor B

The "Z" output is a Logic 1 if F0-F7 are all zeros.
The "OVF" output is a Logic 1 if the result of an arithmetic add, subtract or multiply overflows, that is if the result is greater than 127 or less than -128.
Divide-by-zero will result in an application error message.