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Logic Design Draw Help

Logic Designer - Draw

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Logic Design Draw (LDD) is a graphical WYSIWYG tool that enables a user to quickly create a computer logic schematic diagram and simulate it.

Logic circuits can be very simple, such as and-or logic, or can consist of hundreds of parts.  Both basic parts (logic gates, flip-flops) and MSI (Medium Scale Integration)  building blocks are provided.

Using blocks, large hierarchical designs - such as small computers - can be built.

LDD consists of two linked windows: a Design window (LDD Draw) and a Simulation window (LDD SIM).

For a new design, input signals are created and named, parts are added to the schematic and then connections between signals and parts are made.  At each step, LDD automatically updates the schematic and its layout.

When the schematic is complete, a simulation can be run by pressing the Simulate button. This opens the Simulation window and simulates the design.  As needed the user can edit simulation options and signal bit patterns.  After each change the simulation is automatically re-run.

For an existing design, signals can be added, renamed or deleted; parts can be added or deleted; connections can be changed; and the design can be re-simulated.

The LDD toolbar includes UnDo and ReDo buttons so that any design or simulation change can be removed or restored.  Up to 100 levels of UnDo/ReDo are supported.

Each design can be saved as a text file for later reuse.  LDD and Logic Simulation (SIM) design files are compatible, that is an LDD design file can be opened and edited by SIM and vice-versa.  File data must be in standard ASCII text format.

Schematic Drawing Creation / Editing

1.  EDIT SIGNALS

Signal names or Comparison Words can be added, renamed or deleted by pressing the Signals button.

A typical design will have one or more input signals, an Output signal name, and one or more Comparison words.  The Output signal is the signal/signal group name on the right-hand side of the Output connector.  Comparison words are used by the simulator to check the simulation results.

Names

Names can be any word from 1-32 characters long with the following exceptions:

a. SIM/SYN Section names (IN_OUT_SIGNALS, PARTS, NETLIST, OPTIONS, END_OF_SPEC) are not allowed as signal names

b. Names consisting only of numbers, such as "123", are not allowed; this avoids Signal Name and Netlist number confusion

c. The following characters not allowed in a name: space tab ; : " or character(s) beginning a comment: // -- ' # .   In addition "=" is not allowed for the Output signal.

Name Groups

A Name group can be used to generate from 1 to 4 numbered names and bit-patterns.  The logic states of the bit-patterns must be specified in hexadecimal format, that is characters 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F (decimal values of 0-15).

Name groups are defined for Input signals and the Compare Word by adding "(n:m)" to the end of the name, where 'n' is the starting bit and 'm' is the last bit of the group.
Note: If the Output connector has more than (1) input, a name group is automatically generated for the Output signals during simulation.

Example:

IN_OUT_SIGNALS

   A(0:3)  4 D A 3 1 0;

This will generate signals A(0), A(1), A(2), A(3), each of which can have unique logic 0/1 bit patterns.

Note that the smallest group number, A(0), is the least-significant hexadecimal bit; and that only Logic 0, Logic 1 and Logic x states are supported.  If an 'x' is specified, the hexadecimal (unexpanded) value of the four signals will be an 'x' for that bit/tic time.

If the Timing Format "Expand Hex" box is checked, the Output display will show the four signals separately:

IN_OUT_SIGNALS

   A(0)   0 1 0 1 1 0;

   A(1)   0 0 1 1 0 0;

   A(2)   1 1 0 0 0 0;

   A(3)   0 1 1 0 0 0;

Example file "Decode IR.txt" can be run as an example of a Name Group and Hexadecimal bit patterns.

2.  ADD PARTS

Parts can be added by selecting a part in the Parts list and selecting the number of parts to be added.

Part Type information

Primitive part types:

buf, inv -  The buf (buffer) is non-inverting and can be used to cause simulation skew (delay) on one or more signals.   The inv (inverter) inverts its input signal.

and, or, xor, nand, nor, xnor logic gates

D flip-flops: dff, dff_c, dff_cp.   The dff is a D flip-flop with only a D and Clock input.   The dff_c is a dff with a Clear input.   The dff_cp is a dff with Clear and Preset inputs.

Oscillators: osc2, osc4, osc6, osc8.  These parts are free-running square-wave generators, with a period of 2, 4, 6 or 8 simulation 'tic' times.

Macro and MSI (Medium Scale Integration) part types:  ROM read-only memory, RAM read-write memory, jkff (JK flip-flop), LS74 D flip-flop, LS138 3:8 decoder, LS148 encoder, LS151 multiplexer, LS163 4-bit counter, LS164 8-bit shift register, LS181 4-bit ALU, LS193 4-bit up-down counter, LS194 register.

Refer to Logic Parts Data for part descriptions and function tables.

3.  DELETE PARTS

Parts can be deleted by pressing the Edit Parts/Output button.
This will provide instructions for selecting a part, or open a delete dialog if the part is already selected.

* Delete Part Shortcut: Select (highlight) any output number of the part.  Then press the Delete key or Right-mouse-click and select option "Delete Part".

4.  EDIT PART/OUTPUT CONNECTOR

To change the inputs to a part or the output connector, select (highlight) any output number of the part, or select the output connector '>>'.   Then press the spacebar and follow the instructions in the new window.

Logic gates and, or, xor, nand, nor, xnor can have from 2 to 10 inputs.  For example, if a part has 3 inputs, one input can be deleted or up to 7 inputs can be added.

D flip-flops can have from 2 to 4 inputs (dff, dff_c, dff_cp).  Adding or subtracting inputs will change the flip-flop type.  For example a dff can be changed to a dff_c part by adding one input.

* Edit Shortcut: Select the part or the Output connector.  Then press the spacebar or Right-mouse-click and select option "Edit Inputs".

Recommended Connection Order

The drawing-layout software starts with the Output connector and the parts connected to it.   Then it traces back to find the parts driving the Output connector part, and the parts driving those parts.

For best drawing-layout results when building a circuit, connect the logic parts in this same order, Output connector first.

5.  MACRO BLOCKS

Logic Design Draw can build user-custom Macro blocks (similar to the LS138-LS194 parts) from a logic schematic.  These blocks can contain any or all part types: primitive, MSI or Macro.  This enables construction of very complex functions, such as a small computer.

The design view can be switched between the schematic drawing and the Macro block by clicking on the Schematic or Macro Block buttons. The macro block inputs are the Input Signals of the schematic, and the Macro block outputs are the input signals to the output connector (' >> ') of the schematic.

In the Macro Block mode, the block name can be entered (Edit Block Name), and the input/output signal names of the block can be renamed (Rename Inputs/Rename Outputs)

Once the block is named, it can be added as a part by clicking on the 'Add to Part Library' button. The part is stored in the SSolver\bin\Macros directory and is added to the LDD Parts list.  Note: if more than 50 Macro files are added to the Macros directory, only the first 50 (alphabetically by name) will be active.

An existing  macro can be updated by editing the schematic with the desired changes and then saving the block using the same block name;  this will overwrite the old-design file in the Macros directory.

As an example, one Macro part, "Serial Input_32-bit", is included with a SimpleSolver installation (version 4.4 or later). This block was built from LDD Primitive Example "Serial Input 32-bit NL.txt".

6.  DESIGN COMMENTS

Design comments can be entered or edited by selecting the Edit/Design Comments menu item.
For compatibility with the Logic Design Auto and Logic Simulation tools, an "apostrophe" (') and a space character will be added to the beginning of each comment line before it is added to the design file.

The design file can be viewed and printed by selecting the View/Design File menu.

7.    LIMITS

in signals 0-50 input signals to logic circuit or MSI part
out signals 1-50 inputs to Output connector
comparison words 1-50 data - checks the simulation result
primitive parts 0-1000 total parts per circuit
Macro parts 0-50 User-defined Macro/MSI parts
signal name 1-32 characters
signal waveform 1-1024 characters
  Search

The Search box can be used to highlight signal names, numbers or text in the Output window.  To search, enter the text to be found and then depress the Enter key.  This will highlight up to 100 instances of the Search text.

To clear all highlighting, delete all text in the Search box and depress Enter.

8.  SIMULATE

To open the LDD Simulation window, press the Simulate button.

The LDD Simulation window includes a Help file for Simulation instructions.